The need for ultra low power circuits has forced circuit designers to scale\r\nvoltage supplies into the sub-threshold region where energy per operation is minimized [1].\r\nThe problem with this is that the traditional 6T SRAM bitcell, used for data storage,\r\nbecomes unreliable at voltages below about 700 mV due to process variations and\r\ndecreased device drive strength [2]. In order to achieve reliable operation, new bitcell\r\ntopologies and assist methods have been proposed. This paper provides a comparison of\r\nfour different bitcell topologies using read and write VMIN as the metrics for evaluation. In\r\naddition, read and write assist methods were tested using the periphery voltage scaling\r\ntechniques discussed in [4ââ?¬â??13]. Measurements taken from a 180 nm test chip show read\r\nfunctionality (without assist methods) down to 500 mV and write functionality down to\r\n600 mV. Using assist methods can reduce both read and write VMIN by 100 mV over the\r\nunassisted test case.
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